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1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 figure 1 ? pin configuration for wf2m32-xhx5 top view block diagram 2m x 8 8 i/o 0-7 2m x 8 8 i/o 8-15 2m x 8 8 i/o 16-23 2m x 8 8 i/o 24-31 a 0 - 20 oe# we1# cs1# we2# cs2# we3# cs3# we4# cs4# 2mx32 5v flash module ? organized as 2mx32 ? commercial, industrial, and military temperature ranges ? 5 volt read and write. 5v 10% supply. ? low power cmos ? data# polling and toggle bit feature for detection of program or erase cycle completion. ? supports reading or programming data to a sector not being erased. ? reset# pin resets internal state machine to the read mode. ? built in decoupling caps and multiple ground pins for low noise operation, separate power and ground planes to improve noise immunity * this product is subject to change without notice. note: for programming information refer to flash programming 16m5 application note. features ? access time of 90, 120, 150ns ? packaging: ? 66 pin, pga type, 1.185" square, hermetic ceramic hip (package 401). ? 68 lead, hermetic cqfp (g2u), 22.4mm (0.880") square (package 510) 3.56mm (0.140") height. designed to t jedec 68 lead 0.990" cqfj footprint (figure 3) ? sector architecture ? 32 equal size sectors of 64kbytes per each 2mx8 chip ? any combination of sectors can be erased. also supports full chip erase. ? minimum 100,000 write/erase cycles minimum reset# internally tied to v cc in the hip package for this pin con- guration. see alternate pin con guration with reset# tied to pin 12 for system control of reset (figure 10, page 11). i/o 8 i/o 9 i/o 10 a 14 a 16 a 11 a 0 a 18 i/o 0 i/o 1 i/o 2 we 2# cs 2# gnd i/o 11 a 10 a 9 a 15 v cc cs 1# a 19 i/o 3 i/o 15 i/o 14 i/o 13 i/o 12 oe# a 17 we 1# i/o 7 i/o 6 i/o 5 i/o 4 i/o 24 i/o 25 i/o 26 a 7 a 12 a 20 a 13 a 8 i/o 16 i/o 17 i/o 18 v cc cs 4# we 4# i/o 27 a 4 a 5 a 6 we 3# cs 3# gnd i/o 19 i/o 31 i/o 30 i/o 29 i/o 28 a 1 a 2 a 3 i/o 23 i/o 22 i/o 21 i/o 20 11 22 33 44 55 66 1 12 23 34 45 56 pin description i/o0-31 data inputs/outputs a0-20 address inputs we1-4# write enables cs1-4# chip selects oe# output enable vcc power supply gnd ground
2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 figure 2 ? pin configuration for wf2m32-xg2ux5 block diagram top view the wedc 68 lead g2u cqfp lls the same t and function as the jedec 68 lead cqfj or 68 plcc. but the g2u has the tce and lead inspection advantage of the cqfp form. 2m x 8 8 i/o 0-7 2m x 8 8 i/o 8-15 2m x 8 8 i/o 16-23 2m x 8 8 i/o 24-31 a 0-20 oe# reset# we1# cs1# we2# cs2# we3# cs3# we4# cs4# 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 gnd i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 v cc a11 a12 a13 a14 a15 a16 cs1# oe# cs2# a17 we2# we3# we4# a18 a19 a20 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 reset# a0 a1 a2 a3 a4 a5 cs3# gnd cs4# we1# a6 a7 a8 a9 a10 v cc 0.940" pin description i/o0-31 data inputs/outputs a0-20 address inputs we1-4# write enables cs1-4# chip selects oe# output enable vcc power supply gnd ground reset# reset
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 absolute maximum ratings parameter symbol ratings unit voltage on any pin relative to v ss v t -2.0 to +7.0 v power dissipation p t 8w storage temperature t stg -65 to +125 c short circuit output current i os 100 ma endurance ? write/erase cycles (extended temp) 100,000 min cycles data retention 20 years recommended dc operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v ground v ss 00 0 v input high voltage v ih 2.0 - v cc + 0.5 v input low voltage v il -0.5 - +0.8 v operating temperature (mil.) t a -55 - +125 c operating temperature (ind.) t a -40 - +85 c notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (@ 5mhz). the frequency component typically is less than 2ma/mhz, with oe# at v ih . 2. i cc active while embedded algorithm (program or erase) is in progress. 3. dc test conditions v il = 0.3v, v ih = v cc - 0.3v capacitance t a = +25c, f = 1.0mhz parameter symbol max unit oe# capacitance coe 50 pf we1-4# capacitance hip (pga) cwe 20 pf hip (alternate pinout) cwe 50 pf cqfp g4t cwe 50 pf cqfp g2u cwe 20 pf g2u (alternate pinout) cwe 50 pf cs1-4# capacitance ccs 20 pf data i/o capacitance ci/o 20 pf address input capacitance cad 50 pf this parameter is guaranteed by design but not tested. dc characteristics ? cmos compatible v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol conditions min max unit input leakage current i li v cc = 5.5, v in = gnd to v cc 10 a output leakage current i lox32 v cc = 5.5, v in = gnd to v cc 10 a v cc active current for read (1) i cc1 cs# = v il , oe# = v ih , f = 5mhz 160 ma v cc active current for program or erase (2) i cc2 cs# = v il , oe# = v ih 240 ma v cc standby current i cc3 v cc = 5.5, cs# = v ih , f = 5mhz, reset# = v cc 0.3v 8.0 ma output low voltage v ol i ol = 12.0 ma, v cc = 4.5 0.45 v output high voltage v oh i oh = -2.5 ma, v cc = 4.5 0.85xv cc v low v cc lock-out voltage v lko 3.2 4.2 v
4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 ac characteristics ? write/erase/program operations - we# controlled v cc = 5.0v, -55c t a +125c parameter symbol -90 -120 -150 unit min max min max min max write cycle time t avav t wc 90 120 150 ns chip select setup time t elwl t cs 000ns write enable pulse width t wlwh t wp 45 50 50 ns address setup time t avwl t as 000ns data setup time t dvwh t ds 45 50 50 ns data hold time t whdx t dh 000ns address hold time t wlax t ah 45 50 50 ns write enable pulse width high t whwl t wph 20 20 20 ns duration of byte programming operation (1) t whwh1 300 300 300 s sector erase (2) t whwh2 15 15 15 sec read recovery time before write t ghwl 000 s v cc setup time t vcs 50 50 50 s chip programming time 44 44 44 sec chip erase time (3) 256 256 256 sec output enable hold time (4) t oeh 10 10 10 ns reset# pulse width (5) t rp 500 500 500 ns notes: 1. typical value for t whwh1 is 7 s. 2. typical value for t whwh2 is 1sec. 3. typical value for chip erase time is 32sec. 4. for toggle and data polling. 5. reset# internally tied to v cc for the default pin con guration in the hip package. ac characteristics ? read-only operations v cc = 5.0v, -55c t a +125c parameter symbol -90 -120 -150 unit min max min max min max read cycle time t avav t rc 90 120 150 ns address access time t avqv t acc 90 120 150 ns chip select access time t elqv t ce 90 120 150 ns output enable to output valid t glqv t oe 40 50 55 ns chip select high to output high z (1) t ehqz t df 20 30 35 ns output enable high to output high z (1) t ghqz t df 20 30 35 ns output hold from addresses, cs# or oe# change, whichever is first t axqx t oh 000ns rst low to read mode (1,2) t ready 20 20 20 s notes: 1. guaranteed by design, not tested. 2. reset# internally tied to v cc for the default pin con guration in the hip package.
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 figure 3 ? ac test circuit notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z0 = 75 y. vz is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. ac test conditions parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v current source current source i ol i oh c eff = 50 pf d.u.t. v z 1.5v (bipolar supply) ac characteristics ? write/erase/program operations,cs# controlled v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol -90 -120 -150 unit min max min max min max write cycle time t avav t wc 90 120 150 ns write enable setup time t wlel t ws 000ns chip select pulse width t eleh t cp 45 50 50 ns address setup time t avel t as 000ns data setup time t dveh t ds 45 50 50 ns data hold time t ehdx t dh 000ns address hold time t elax t ah 45 50 50 ns chip select pulse width high t ehel t cph 20 20 20 ns duration of byte programming operation (1) t whwh1 300 300 300 s sector erase time (2) t whwh2 15 15 15 sec read recovery time t ghel 000 s chip programming time 44 44 44 sec chip erase time (3) 256 256 256 sec output enable hold time (4) t oeh 10 10 10 ns notes: 1. typical value for twhwh1 is 7 s. 2. typical value for twhwh2 is 1sec. 3. typical value for chip erase time is 32sec. 4. for toggle and data polling. figure 4 ? reset timing diagram reset# t rp t ready
6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 figure 5 ? ac waveforms for read operations cs# oe# we#
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d7# is the output of the complement of the data written to each chip. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. figure 6 ? write/erase/program operation, we# controlled cs# data# polling oe# d 7 # we#
8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 figure 7 ? ac waveforms chip/sector erase operations note: 1. sa is the sector address for sector erase. cs# oe# we#
9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 figure 8 ? ac waveforms for data# polling during embedded algorithm operations cs# oe# we# t oe t ce t ch t oh d7# d7 = valid data high z d0-d6 = invalid d0-d7 valid data t df d7 d0-d6 t oeh t whwh 1 or 2 data
10 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 notes: 1. pa represents the address of the memory location to be programmed. 2. pd represents the data to be programmed at byte address. 3. d7# is the output of the complement of the data written to each chip. 4. d out is the output of the data written to the device. 5. figure indicates the last two bus cycles of a four bus cycle sequence. figure 9 ? alternate cs# controlled programming operation timings cs# data# polling oe# d 7 # we# t ghel t cp t ws t cph
11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 figure 10 ? alternate pin configuration for wf2m32i-xhx5 pin description i/o 0-31 data inputs/outputs a 0-20 address inputs we# write enable cs 1-4 # chip selects oe# output enable v cc power supply gnd ground reset# reset top view block diagram figure 11 ? alternate pin configuration for wf2m32u-xg2ux5 block diagram top view the wedc 68 lead g2u cqfp lls the same t and function as the jedec 68 lead cqfj or 68 plcc. but the g2u has the tce and lead inspection advantage of the cqfp form. 2m x 8 8 i/o 0-7 2m x 8 8 i/o 8-15 2m x 8 8 i/o 16-23 2m x 8 8 i/o 24-31 a 0-20 oe# reset# cs# we# 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 gnd i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 v cc a11 a12 a13 a14 a15 a16 cs# oe# nc a17 nc nc nc a18 a19 a20 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 reset# a0 a1 a2 a3 a4 a5 nc gnd nc we# a6 a7 a8 a9 a10 v cc pin description i/o 0-31 data inputs/outputs a 0-20 address inputs we# write enable cs# chip select oe# output enable v cc power supply gnd ground reset# reset 0.940" i/o 8 i/o 9 i/o 10 a 14 a 16 a 11 a 0 a 18 i/o 0 i/o 1 i/o 2 reset# cs 2# gnd i/o 11 a 10 a 9 a 15 v cc cs 1 # a 19 i/o 3 i/o 15 i/o 14 i/o 13 i/o 12 oe# a 17 we# i/o 7 i/o 6 i/o 5 i/o 4 i/o 24 i/o 25 i/o 26 a 7 a 12 nc a 13 a 8 i/o 16 i/o 17 i/o 18 v cc cs 4 # nc i/o 27 a 4 a 5 a 6 a 20 cs 3 # gnd i/o 19 i/o 31 i/o 30 i/o 29 i/o 28 a 1 a 2 a 3 i/o 23 i/o 22 i/o 21 i/o 20 11 22 33 44 55 66 1 12 23 34 45 56 2m x 8 8 i/o 0-7 cs1# cs2# cs3# cs4# 2m x 8 8 i/o 8-15 2m x 8 8 i/o 16-23 2m x 8 8 i/o 24-31 a 0 - 20 oe# we# reset#
12 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 figure 12 ? pin configuration for wf2m32i-xg2ux5 pin description i/o 0-31 data inputs/outputs a 0-20 address inputs we# write enable cs 1-4 # chip selects oe# output enable v cc power supply gnd ground reset# reset top view block diagram 2m x 8 8 i/o 0-7 cs1# cs2# cs3# cs4# 2m x 8 8 i/o 8-15 2m x 8 8 i/o 16-23 2m x 8 8 i/o 24-31 a 0 - 20 oe# we# reset# the wedc 68 lead g2u cqfp lls the same t and function as the jedec 68 lead cqfj or 68 plcc. but the g2u has the tce and lead inspection advantage of the cqfp form. 0.940" 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 gnd i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 v cc a11 a12 a13 a14 a15 a16 cs1# oe# cs2# a17 nc nc nc a18 a19 a20 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 reset# a0 a1 a2 a3 a4 a5 cs3# gnd cs4# we# a6 a7 a8 a9 a10 v cc
13 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 30.1 (1.185) 0.38 (0.015) sq 1.27 (0.050) 0.1 (0.005) 0.46 (0.018) 0.05 (0.002) dia 1.27 (0.050) typ dia 0.76 (0.030) 0.1 (0.005) 25.4 (1.0) typ 25.4 (1.0) typ 15.24 (0.600) typ 6.22 (0.245) max pin 1 identifier square pad on bottom 3.81 (0.150) 0.1 (0.005) 2.54 (0.100) typ package 401: 66 pin, pga type, ceramic hex-in-line package, hip (h) all linear dimensions are millimeters and parenthetically in inches
14 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 package 510: 68 lead, ceramic quad flat pack, cqfp (g2u) all linear dimensions are millimeters and parenthetically in inches 0.940" typ the wedc 68 lead g2u cqfp lls the same t and function as the jedec 68 lead cqfj or 68 plcc. but the g2u has the tce and lead inspection advantage of the cqfp form.
15 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m32-xxx5 october 2004 rev. 5 lead finish: blank = gold plated leads a = solder dip leads v pp programming voltage 5 = 5 v device grade: q = compliant -55c to +125c m = military -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c package type: h = ceramic hex in line package, hip (package 401) g2u = 22.4mm ceramic quad flat pack, cqfp (package 510) access time (ns) improvement mark ? for hip package blank = 4cs# and 4we# i = 4cs# and 1we#, reset# ? for g2u package blank = 4cs# and 4we# u = 1cs# and 1we# i = 4cs# and 1we#, reset# organization, 2m x 32 user con gurable as 4m x 16 or 8m x 8 (except wf2m32u-xg2ux which is 32 bit wide only.) flash white electronic designs corp. ordering information w f 2m32 x - xxx x x 5 x

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